PDITarget_EnableTargetPDI();\r
\r
/* Store the RESET key into the RESET PDI register to keep the XMEGA in reset */\r
- PDITarget_SendByte(PDI_CMD_STCS | PD_RESET_REG); \r
+ PDITarget_SendByte(PDI_CMD_STCS | PDI_RESET_REG); \r
PDITarget_SendByte(PDI_RESET_KEY);\r
\r
/* Enable access to the XPROG NVM bus by sending the documented NVM access key to the device */\r
PDITarget_SendByte(PDI_CMD_KEY); \r
- for (uint8_t i = 0; i < sizeof(PDI_NVMENABLE_KEY); i++)\r
- PDITarget_SendByte(PDI_NVMENABLE_KEY[i]);\r
+ for (uint8_t i = sizeof(PDI_NVMENABLE_KEY); i > 0; i--)\r
+ PDITarget_SendByte(PDI_NVMENABLE_KEY[i - 1]);\r
\r
- /* Poll the STATUS register to check to see if NVM access has been enabled */\r
- uint8_t NVMAttemptsRemaining = 200;\r
- while (NVMAttemptsRemaining--)\r
- {\r
- _delay_ms(1);\r
- PDITarget_SendByte(PDI_CMD_LDCS | PD_STATUS_REG);\r
-\r
- if (PDITarget_ReceiveByte() & PDI_STATUS_NVM)\r
- break;\r
- }\r
+ /* Wait until the NVM bus becomes active */\r
+ bool NVMBusEnabled = PDITarget_WaitWhileNVMBusBusy();\r
\r
Endpoint_Write_Byte(CMD_XPROG);\r
Endpoint_Write_Byte(XPRG_CMD_ENTER_PROGMODE);\r
- Endpoint_Write_Byte(NVMAttemptsRemaining ? XPRG_ERR_OK : XPRG_ERR_FAILED);\r
+ Endpoint_Write_Byte(NVMBusEnabled ? XPRG_ERR_OK : XPRG_ERR_FAILED);\r
Endpoint_ClearIN();\r
}\r
\r
Endpoint_SetEndpointDirection(ENDPOINT_DIR_IN);\r
\r
/* Clear the RESET key into the RESET PDI register to allow the XMEGA to run */\r
- PDITarget_SendByte(PDI_CMD_STCS | PD_RESET_REG); \r
+ PDITarget_SendByte(PDI_CMD_STCS | PDI_RESET_REG); \r
PDITarget_SendByte(0x00);\r
\r
PDITarget_DisableTargetPDI();\r
Endpoint_ClearOUT();\r
Endpoint_SetEndpointDirection(ENDPOINT_DIR_IN);\r
\r
- // TODO: Send read command here via PDI protocol\r
+ if (ReadMemory_XPROG_Params.MemoryType == XPRG_MEM_TYPE_USERSIG)\r
+ {\r
+ PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_1BYTE << 2));\r
+ PDITarget_SendAddress(DATAMEM_BASE | DATAMEM_NVM_CMD);\r
+ PDITarget_SendByte(NVM_CMD_READUSERSIG);\r
+\r
+ \r
+ }\r
\r
Endpoint_Write_Byte(CMD_XPROG);\r
Endpoint_Write_Byte(XPRG_CMD_READ_MEM);\r
static void PDIProtocol_ReadCRC(void)\r
{\r
uint8_t ReturnStatus = XPRG_ERR_OK;\r
-\r
- uint8_t CRCType = Endpoint_Read_Byte();\r
\r
+ struct\r
+ {\r
+ uint8_t CRCType;\r
+ } ReadCRC_XPROG_Params;\r
+ \r
+ Endpoint_Read_Stream_LE(&ReadCRC_XPROG_Params, sizeof(ReadCRC_XPROG_Params));\r
Endpoint_ClearOUT();\r
Endpoint_SetEndpointDirection(ENDPOINT_DIR_IN);\r
\r
uint32_t MemoryCRC = 0;\r
+ uint8_t CRCReadCommand;\r
+\r
+ if (ReadCRC_XPROG_Params.CRCType == XPRG_CRC_APP)\r
+ CRCReadCommand = NVM_CMD_APPCRC;\r
+ else if (ReadCRC_XPROG_Params.CRCType == XPRG_CRC_BOOT)\r
+ CRCReadCommand = NVM_CMD_BOOTCRC;\r
+ else\r
+ CRCReadCommand = NVM_CMD_FLASHCRC;\r
+ \r
+ /* Set the NVM command to the correct CRC read command */\r
+ PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_1BYTE << 2));\r
+ PDITarget_SendAddress(DATAMEM_BASE | DATAMEM_NVM_CMD);\r
+ PDITarget_SendByte(CRCReadCommand);\r
+\r
+ /* Set CMDEX bit in NVM CTRLA register to start the CRC generation */\r
+ PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_1BYTE << 2));\r
+ PDITarget_SendAddress(DATAMEM_BASE | DATAMEM_NVM_CTRLA);\r
+ PDITarget_SendByte(1 << 0);\r
+\r
+ /* Wait until the NVM bus and controller is no longer busy */\r
+ PDITarget_WaitWhileNVMBusBusy();\r
+ PDITarget_WaitWhileNVMControllerBusy();\r
\r
- // TODO: Read device CRC for desired memory via PDI protocol\r
+ /* Read the three byte generated CRC value */\r
+ PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_3BYTES << 2));\r
+ PDITarget_SendAddress(DATAMEM_BASE | DATAMEM_NVM_DAT0);\r
+ MemoryCRC = PDITarget_ReceiveByte();\r
+ MemoryCRC |= ((uint16_t)PDITarget_ReceiveByte() << 8);\r
+ MemoryCRC |= ((uint32_t)PDITarget_ReceiveByte() << 16);\r
\r
Endpoint_Write_Byte(CMD_XPROG);\r
Endpoint_Write_Byte(XPRG_CMD_CRC);\r