+/** Enables the target's PDI interface, holding the target in reset until PDI mode is exited. */\r
+void PDITarget_EnableTargetPDI(void)\r
+{\r
+#if defined(PDI_VIA_HARDWARE_USART)\r
+ /* Set Tx and XCK as outputs, Rx as input */\r
+ DDRD |= (1 << 5) | (1 << 3);\r
+ DDRD &= ~(1 << 2);\r
+ \r
+ /* Set DATA line high for at least 90ns to disable /RESET functionality */\r
+ PORTD |= (1 << 3);\r
+ asm volatile ("NOP"::);\r
+ asm volatile ("NOP"::);\r
+ \r
+ /* Set up the synchronous USART for XMEGA communications - \r
+ 8 data bits, even parity, 2 stop bits */\r
+ UBRR1 = (F_CPU / 1000000UL);\r
+ UCSR1B = (1 << TXEN1);\r
+ UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);\r
+\r
+ /* Send two BREAKs of 12 bits each to enable PDI interface (need at least 16 idle bits) */\r
+ PDITarget_SendBreak();\r
+ PDITarget_SendBreak();\r
+#else\r
+ /* Set DATA and CLOCK lines to outputs */\r
+ BITBANG_PDIDATA_DDR |= BITBANG_PDIDATA_MASK;\r
+ BITBANG_PDICLOCK_DDR |= BITBANG_PDICLOCK_MASK;\r
+ \r
+ /* Set DATA line high for at least 90ns to disable /RESET functionality */\r
+ BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;\r
+ asm volatile ("NOP"::);\r
+ asm volatile ("NOP"::);\r
+\r
+ /* Fire timer compare ISR every 100 cycles to manage the software USART */\r
+ OCR1A = 80;\r
+ TCCR1B = (1 << WGM12) | (1 << CS10);\r
+ TIMSK1 = (1 << OCIE1A);\r
+ \r
+ PDITarget_SendBreak();\r
+ PDITarget_SendBreak();\r
+#endif\r
+}\r