Make sure that long reads are aborted early if the connection times out while waiting...

[pub/USBasp.git] / Projects / AVRISP-MKII / Lib / XPROG / XPROGTarget.c

diff --git a/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c b/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c
index bfc2e82..e75adbe 100644 (file)
--- a/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c
+++ b/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c
@@ -156,8 +156,7 @@ void XPROGTarget_EnableTargetPDI(void)
        PORTD |= (1 << 3);\r
        _delay_us(1);\r
        \r
        PORTD |= (1 << 3);\r
        _delay_us(1);\r
        \r

-       /* Set up the synchronous USART for XMEGA communications - \r
-          8 data bits, even parity, 2 stop bits */\r
+       /* Set up the synchronous USART for XMEGA communications - 8 data bits, even parity, 2 stop bits */\r

        UBRR1  = (F_CPU / XPROG_HARDWARE_SPEED);\r
        UCSR1B = (1 << TXEN1);\r
        UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);\r
        UBRR1  = (F_CPU / XPROG_HARDWARE_SPEED);\r
        UCSR1B = (1 << TXEN1);\r
        UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);\r


@@ -171,10 +170,9 @@ void XPROGTarget_EnableTargetPDI(void)
        _delay_us(1);\r
 \r
        /* Fire timer compare channel A ISR to manage the software USART */\r
        _delay_us(1);\r
 \r
        /* Fire timer compare channel A ISR to manage the software USART */\r

-       OCR1A   = BITS_BETWEEN_USART_CLOCKS;\r
-       OCR1B   = BITS_BETWEEN_USART_CLOCKS;\r
-       TCCR1B  = (1 << WGM12) | (1 << CS10);\r
-       TIMSK1  = (1 << OCIE1A);\r
+       OCR1A  = BITS_BETWEEN_USART_CLOCKS;\r
+       TCCR1B = (1 << WGM12) | (1 << CS10);\r
+       TIMSK1 = (1 << OCIE1A);\r

 #endif\r
 \r
        /* Send two BREAKs of 12 bits each to enable PDI interface (need at least 16 idle bits) */\r
 #endif\r
 \r
        /* Send two BREAKs of 12 bits each to enable PDI interface (need at least 16 idle bits) */\r


@@ -197,8 +195,7 @@ void XPROGTarget_EnableTargetTPI(void)
        DDRD |=  (1 << 5) | (1 << 3);\r
        DDRD &= ~(1 << 2);\r
                \r
        DDRD |=  (1 << 5) | (1 << 3);\r
        DDRD &= ~(1 << 2);\r
                \r

-       /* Set up the synchronous USART for TINY communications - \r
-          8 data bits, even parity, 2 stop bits */\r
+       /* Set up the synchronous USART for TINY communications - 8 data bits, even parity, 2 stop bits */\r

        UBRR1  = (F_CPU / XPROG_HARDWARE_SPEED);\r
        UCSR1B = (1 << TXEN1);\r
        UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);\r
        UBRR1  = (F_CPU / XPROG_HARDWARE_SPEED);\r
        UCSR1B = (1 << TXEN1);\r
        UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);\r


@@ -211,9 +208,9 @@ void XPROGTarget_EnableTargetTPI(void)
        BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;\r
 \r
        /* Fire timer capture channel ISR to manage the software USART */\r
        BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;\r
 \r
        /* Fire timer capture channel ISR to manage the software USART */\r

-       ICR1    = BITS_BETWEEN_USART_CLOCKS;\r
-       TCCR1B  = (1 << WGM13) | (1 << WGM12) | (1 << CS10);\r
-       TIMSK1  = (1 << ICIE1);\r
+       ICR1   = BITS_BETWEEN_USART_CLOCKS;\r
+       TCCR1B = (1 << WGM13) | (1 << WGM12) | (1 << CS10);\r
+       TIMSK1 = (1 << ICIE1);\r

 #endif\r
 \r
        /* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */\r
 #endif\r
 \r
        /* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */\r


@@ -341,6 +338,9 @@ uint8_t XPROGTarget_ReceiveByte(void)
                }       \r
        }\r
        \r
                }       \r
        }\r
        \r

+       if (TimeoutMSRemaining)\r
+         TimeoutMSRemaining = COMMAND_TIMEOUT_MS;\r
+\r

        return UDR1;\r
 #else\r
        /* Wait until a byte has been received before reading */\r
        return UDR1;\r
 #else\r
        /* Wait until a byte has been received before reading */\r


@@ -402,8 +402,15 @@ static void XPROGTarget_SetTxMode(void)
                \r
        IsSending = true;\r
 #else\r
                \r
        IsSending = true;\r
 #else\r

-       while (SoftUSART_BitCount);\r
-\r
+       while (SoftUSART_BitCount && TimeoutMSRemaining)\r
+       {       \r
+               if (TIFR0 & (1 << OCF0A))\r
+               {\r
+                       TIFR0 |= (1 << OCF0A);\r
+                       TimeoutMSRemaining--;\r
+               }\r
+       }\r
+       \r

        /* Wait for a full cycle of the clock */\r
        SoftUSART_Data     = 0x0001;\r
        SoftUSART_BitCount = 1;\r
        /* Wait for a full cycle of the clock */\r
        SoftUSART_Data     = 0x0001;\r
        SoftUSART_BitCount = 1;\r


@@ -436,28 +443,46 @@ static void XPROGTarget_SetRxMode(void)
        DDRD   &= ~(1 << 3);\r
        PORTD  &= ~(1 << 3);\r
 #else\r
        DDRD   &= ~(1 << 3);\r
        PORTD  &= ~(1 << 3);\r
 #else\r

-       while (SoftUSART_BitCount);\r
+       while (SoftUSART_BitCount && TimeoutMSRemaining)\r
+       {       \r
+               if (TIFR0 & (1 << OCF0A))\r
+               {\r
+                       TIFR0 |= (1 << OCF0A);\r
+                       TimeoutMSRemaining--;\r
+               }\r
+       }\r

 \r
        if (XPROG_SelectedProtocol == XPRG_PROTOCOL_PDI)\r
        {\r
                BITBANG_PDIDATA_DDR  &= ~BITBANG_PDIDATA_MASK;\r
                BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;\r
 \r
        if (XPROG_SelectedProtocol == XPRG_PROTOCOL_PDI)\r
        {\r
                BITBANG_PDIDATA_DDR  &= ~BITBANG_PDIDATA_MASK;\r
                BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;\r

+\r
+               /* Wait until DATA line has been pulled up to idle by the target */\r
+               while (!(BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK) && TimeoutMSRemaining)\r
+               {\r
+                       /* Manage software timeout */\r
+                       if (TIFR0 & (1 << OCF0A))\r
+                       {\r
+                               TIFR0 |= (1 << OCF0A);\r
+                               TimeoutMSRemaining--;\r
+                       }\r
+               }\r

        }\r
        else\r
        {\r
                BITBANG_TPIDATA_DDR  &= ~BITBANG_TPIDATA_MASK;\r
        }\r
        else\r
        {\r
                BITBANG_TPIDATA_DDR  &= ~BITBANG_TPIDATA_MASK;\r

-               BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK;  \r
-       }\r
-       \r
-       /* Wait until DATA line has been pulled up to idle by the target */\r
-       while (!(BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK) && TimeoutMSRemaining)\r
-       {\r
-               /* Manage software timeout */\r
-               if (TIFR0 & (1 << OCF0A))\r
+               BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK;\r
+\r
+               /* Wait until DATA line has been pulled up to idle by the target */\r
+               while (!(BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK) && TimeoutMSRemaining)\r

                {\r
                {\r

-                       TIFR0 |= (1 << OCF0A);\r
-                       TimeoutMSRemaining--;\r
-               }\r
+                       /* Manage software timeout */\r
+                       if (TIFR0 & (1 << OCF0A))\r
+                       {\r
+                               TIFR0 |= (1 << OCF0A);\r
+                               TimeoutMSRemaining--;\r
+                       }\r
+               }       \r

        }       \r
 #endif\r
 \r
        }       \r
 #endif\r
 \r