+ if (option == USBASP_ISP_SCK_AUTO)
+ option = USBASP_ISP_SCK_375;
+
+ if (option >= USBASP_ISP_SCK_93_75) {
+ ispTransmit = ispTransmit_hw;
+ sck_spsr = 0;
+
+ switch (option) {
+
+ case USBASP_ISP_SCK_1500:
+ /* enable SPI, master, 1.5MHz, XTAL/8 */
+ sck_spcr = (1 << SPE) | (1 << MSTR) | (1 << SPR0);
+ sck_spsr = (1 << SPI2X);
+ case USBASP_ISP_SCK_750:
+ /* enable SPI, master, 750kHz, XTAL/16 */
+ sck_spcr = (1 << SPE) | (1 << MSTR) | (1 << SPR0);
+ break;
+ case USBASP_ISP_SCK_375:
+ default:
+ /* enable SPI, master, 375kHz, XTAL/32 (default) */
+ sck_spcr = (1 << SPE) | (1 << MSTR) | (1 << SPR1);
+ sck_spsr = (1 << SPI2X);
+ break;
+ case USBASP_ISP_SCK_187_5:
+ /* enable SPI, master, 187.5kHz XTAL/64 */
+ sck_spcr = (1 << SPE) | (1 << MSTR) | (1 << SPR1);
+ break;
+ case USBASP_ISP_SCK_93_75:
+ /* enable SPI, master, 93.75kHz XTAL/128 */
+ sck_spcr = (1 << SPE) | (1 << MSTR) | (1 << SPR1) | (1 << SPR0);
+ break;
+ }
+
+ } else {
+ ispTransmit = ispTransmit_sw;
+ switch (option) {
+
+ case USBASP_ISP_SCK_32:
+ sck_sw_delay = 3;
+
+ break;
+ case USBASP_ISP_SCK_16:
+ sck_sw_delay = 6;
+
+ break;
+ case USBASP_ISP_SCK_8:
+ sck_sw_delay = 12;
+
+ break;
+ case USBASP_ISP_SCK_4:
+ sck_sw_delay = 24;
+
+ break;
+ case USBASP_ISP_SCK_2:
+ sck_sw_delay = 48;
+
+ break;
+ case USBASP_ISP_SCK_1:
+ sck_sw_delay = 96;
+
+ break;
+ case USBASP_ISP_SCK_0_5:
+ sck_sw_delay = 192;
+
+ break;
+ }
+ }