Fixed compilation error in the AudioInput demos when MICROPHONE_BIASED_TO_HALF_RAIL...

[pub/USBasp.git] / Projects / AVRISP-MKII / Lib / XPROG / XPROGTarget.c

diff --git a/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c b/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c
index 85a7504..bfc2e82 100644 (file)
--- a/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c
+++ b/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c
@@ -53,12 +53,13 @@ volatile uint16_t           SoftUSART_Data;
 ISR(TIMER1_COMPA_vect, ISR_BLOCK)\r
 {\r
        /* Toggle CLOCK pin in a single cycle (see AVR datasheet) */\r
 ISR(TIMER1_COMPA_vect, ISR_BLOCK)\r
 {\r
        /* Toggle CLOCK pin in a single cycle (see AVR datasheet) */\r

-       BITBANG_PDICLOCK_PIN |= BITBANG_PDICLOCK_MASK;\r
+       BITBANG_PDICLOCK_PIN = BITBANG_PDICLOCK_MASK;\r

 \r
        /* If not sending or receiving, just exit */\r
        if (!(SoftUSART_BitCount))\r
          return;\r
 \r
 \r
        /* If not sending or receiving, just exit */\r
        if (!(SoftUSART_BitCount))\r
          return;\r
 \r

+       /* Check to see if we are at a rising or falling edge of the clock */\r

        if (BITBANG_PDICLOCK_PORT & BITBANG_PDICLOCK_MASK)\r
        {\r
                /* If at rising clock edge and we are in send mode, abort */\r
        if (BITBANG_PDICLOCK_PORT & BITBANG_PDICLOCK_MASK)\r
        {\r
                /* If at rising clock edge and we are in send mode, abort */\r


@@ -79,10 +80,6 @@ ISR(TIMER1_COMPA_vect, ISR_BLOCK)
        }\r
        else\r
        {\r
        }\r
        else\r
        {\r

-               /* If not sending or receiving, just exit */\r
-               if (!(SoftUSART_BitCount))\r
-                 return;\r
-\r

                /* If at falling clock edge and we are in receive mode, abort */\r
                if (!IsSending)\r
                  return;\r
                /* If at falling clock edge and we are in receive mode, abort */\r
                if (!IsSending)\r
                  return;\r


@@ -102,7 +99,7 @@ ISR(TIMER1_COMPA_vect, ISR_BLOCK)
 ISR(TIMER1_CAPT_vect, ISR_BLOCK)\r
 {\r
        /* Toggle CLOCK pin in a single cycle (see AVR datasheet) */\r
 ISR(TIMER1_CAPT_vect, ISR_BLOCK)\r
 {\r
        /* Toggle CLOCK pin in a single cycle (see AVR datasheet) */\r

-       BITBANG_TPICLOCK_PIN |= BITBANG_TPICLOCK_MASK;\r
+       BITBANG_TPICLOCK_PIN = BITBANG_TPICLOCK_MASK;\r

 \r
        /* If not sending or receiving, just exit */\r
        if (!(SoftUSART_BitCount))\r
 \r
        /* If not sending or receiving, just exit */\r
        if (!(SoftUSART_BitCount))\r


@@ -161,7 +158,7 @@ void XPROGTarget_EnableTargetPDI(void)
        \r
        /* Set up the synchronous USART for XMEGA communications - \r
           8 data bits, even parity, 2 stop bits */\r
        \r
        /* Set up the synchronous USART for XMEGA communications - \r
           8 data bits, even parity, 2 stop bits */\r

-       UBRR1  = (F_CPU / 500000UL);\r
+       UBRR1  = (F_CPU / XPROG_HARDWARE_SPEED);\r

        UCSR1B = (1 << TXEN1);\r
        UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);\r
 #else\r
        UCSR1B = (1 << TXEN1);\r
        UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);\r
 #else\r


@@ -202,7 +199,7 @@ void XPROGTarget_EnableTargetTPI(void)
                \r
        /* Set up the synchronous USART for TINY communications - \r
           8 data bits, even parity, 2 stop bits */\r
                \r
        /* Set up the synchronous USART for TINY communications - \r
           8 data bits, even parity, 2 stop bits */\r

-       UBRR1  = (F_CPU / 500000UL);\r
+       UBRR1  = (F_CPU / XPROG_HARDWARE_SPEED);\r

        UCSR1B = (1 << TXEN1);\r
        UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);\r
 #else\r
        UCSR1B = (1 << TXEN1);\r
        UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);\r
 #else\r


@@ -231,26 +228,18 @@ void XPROGTarget_DisableTargetPDI(void)
        XPROGTarget_SetRxMode();\r
 \r
 #if defined(XPROG_VIA_HARDWARE_USART)\r
        XPROGTarget_SetRxMode();\r
 \r
 #if defined(XPROG_VIA_HARDWARE_USART)\r

-       /* Set /RESET high for a one millisecond to ensure target device is restarted */\r
-       PORTD |= (1 << 5);\r
-       _delay_ms(1);\r
-\r

        /* Turn off receiver and transmitter of the USART, clear settings */\r
        /* Turn off receiver and transmitter of the USART, clear settings */\r

-       UCSR1A |= (1 << TXC1) | (1 << RXC1);\r
+       UCSR1A  = ((1 << TXC1) | (1 << RXC1));\r

        UCSR1B  = 0;\r
        UCSR1C  = 0;\r
 \r
        UCSR1B  = 0;\r
        UCSR1C  = 0;\r
 \r

-       /* Set all USART lines as input, tristate */\r
+       /* Tristate all pins */\r

        DDRD  &= ~((1 << 5) | (1 << 3));\r
        PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));\r
 #else\r
        /* Turn off software USART management timer */\r
        TCCR1B = 0;\r
 \r
        DDRD  &= ~((1 << 5) | (1 << 3));\r
        PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));\r
 #else\r
        /* Turn off software USART management timer */\r
        TCCR1B = 0;\r
 \r

-       /* Set /RESET high for a one millisecond to ensure target device is restarted */\r
-       BITBANG_PDICLOCK_PORT |= BITBANG_PDICLOCK_MASK;\r
-       _delay_ms(1);\r
-\r

        /* Set DATA and CLOCK lines to inputs */\r
        BITBANG_PDIDATA_DDR   &= ~BITBANG_PDIDATA_MASK;\r
        BITBANG_PDICLOCK_DDR  &= ~BITBANG_PDICLOCK_MASK;\r
        /* Set DATA and CLOCK lines to inputs */\r
        BITBANG_PDIDATA_DDR   &= ~BITBANG_PDIDATA_MASK;\r
        BITBANG_PDICLOCK_DDR  &= ~BITBANG_PDICLOCK_MASK;\r