Added ENABLE_TELNET_SERVER compile time option to the Webserver project to disable...

[pub/USBasp.git] / Projects / AVRISP-MKII / Lib / XPROG / XPROGTarget.c

diff --git a/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c b/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c
index 85a7504..957084c 100644 (file)
--- a/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c
+++ b/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c
@@ -53,12 +53,13 @@ volatile uint16_t           SoftUSART_Data;
 ISR(TIMER1_COMPA_vect, ISR_BLOCK)\r
 {\r
        /* Toggle CLOCK pin in a single cycle (see AVR datasheet) */\r
 ISR(TIMER1_COMPA_vect, ISR_BLOCK)\r
 {\r
        /* Toggle CLOCK pin in a single cycle (see AVR datasheet) */\r

-       BITBANG_PDICLOCK_PIN |= BITBANG_PDICLOCK_MASK;\r
+       BITBANG_PDICLOCK_PIN = BITBANG_PDICLOCK_MASK;\r

 \r
        /* If not sending or receiving, just exit */\r
        if (!(SoftUSART_BitCount))\r
          return;\r
 \r
 \r
        /* If not sending or receiving, just exit */\r
        if (!(SoftUSART_BitCount))\r
          return;\r
 \r

+       /* Check to see if we are at a rising or falling edge of the clock */\r

        if (BITBANG_PDICLOCK_PORT & BITBANG_PDICLOCK_MASK)\r
        {\r
                /* If at rising clock edge and we are in send mode, abort */\r
        if (BITBANG_PDICLOCK_PORT & BITBANG_PDICLOCK_MASK)\r
        {\r
                /* If at rising clock edge and we are in send mode, abort */\r


@@ -102,7 +103,7 @@ ISR(TIMER1_COMPA_vect, ISR_BLOCK)
 ISR(TIMER1_CAPT_vect, ISR_BLOCK)\r
 {\r
        /* Toggle CLOCK pin in a single cycle (see AVR datasheet) */\r
 ISR(TIMER1_CAPT_vect, ISR_BLOCK)\r
 {\r
        /* Toggle CLOCK pin in a single cycle (see AVR datasheet) */\r

-       BITBANG_TPICLOCK_PIN |= BITBANG_TPICLOCK_MASK;\r
+       BITBANG_TPICLOCK_PIN = BITBANG_TPICLOCK_MASK;\r

 \r
        /* If not sending or receiving, just exit */\r
        if (!(SoftUSART_BitCount))\r
 \r
        /* If not sending or receiving, just exit */\r
        if (!(SoftUSART_BitCount))\r