volatile uint16_t SoftUSART_Data;\r
volatile uint8_t SoftUSART_BitCount;\r
\r
-ISR(TIMER0_COMPA_vect, ISR_BLOCK)\r
+ISR(TIMER1_COMPA_vect, ISR_BLOCK)\r
{\r
/* Toggle CLOCK pin in a single cycle (see AVR datasheet) */\r
BITBANG_PDICLOCK_PIN |= BITBANG_PDICLOCK_MASK;\r
asm volatile ("NOP"::);\r
asm volatile ("NOP"::);\r
\r
- /* Fire timer compare ISR every 50 cycles to manage the software USART */\r
- OCR0A = 50;\r
- TCCR0A = (1 << WGM01);\r
- TCCR0B = (1 << CS00);\r
- TIMSK0 = (1 << OCIE0A);\r
+ /* Fire timer compare ISR every 100 cycles to manage the software USART */\r
+ OCR1A = 100;\r
+ TCCR1B = (1 << WGM12) | (1 << CS10);\r
+ TIMSK1 = (1 << OCIE1A);\r
\r
PDITarget_SendBreak();\r
PDITarget_SendBreak();\r
#endif\r
}\r
\r
+bool PDITarget_WaitWhileNVMBusBusy(void)\r
+{\r
+ TCNT0 = 0;\r
+\r
+ /* Poll the STATUS register to check to see if NVM access has been enabled */\r
+ while (TCNT0 < PDI_NVM_TIMEOUT_MS)\r
+ {\r
+ /* Send the LDCS command to read the PDI STATUS register to see the NVM bus is active */\r
+ PDITarget_SendByte(PDI_CMD_LDCS | PDI_STATUS_REG);\r
+ if (PDITarget_ReceiveByte() & PDI_STATUS_NVM)\r
+ return true;\r
+ }\r
+ \r
+ return false;\r
+}\r
+\r
#endif\r