\r
void NVMTarget_SendNVMRegAddress(uint8_t Register)\r
{\r
+ /* Determine the absolute register address from the NVM base memory address and the NVM register address */\r
uint32_t Address = XPROG_Param_NVMBase | Register;\r
\r
+ /* Send the calculated 32-bit address to the target, LSB first */\r
PDITarget_SendByte(Address & 0xFF);\r
PDITarget_SendByte(Address >> 8);\r
PDITarget_SendByte(Address >> 16);\r
\r
void NVMTarget_SendAddress(uint32_t AbsoluteAddress)\r
{\r
+ /* Send the given 32-bit address to the target, LSB first */\r
PDITarget_SendByte(AbsoluteAddress & 0xFF);\r
PDITarget_SendByte(AbsoluteAddress >> 8);\r
PDITarget_SendByte(AbsoluteAddress >> 16);\r
PDITarget_SendByte(AbsoluteAddress >> 24);\r
}\r
\r
-bool NVMTarget_WaitWhileNVMBusBusy(void)\r
+bool NVMTarget_WaitWhileNVMControllerBusy(void)\r
{\r
- uint8_t AttemptsRemaining = 255;\r
+ TCNT0 = 0;\r
\r
- /* Poll the STATUS register to check to see if NVM access has been enabled */\r
- while (AttemptsRemaining--)\r
- {\r
- PDITarget_SendByte(PDI_CMD_LDCS | PDI_STATUS_REG);\r
- if (PDITarget_ReceiveByte() & PDI_STATUS_NVM)\r
- return true;\r
- }\r
- \r
- return false;\r
-}\r
-\r
-void NVMTarget_WaitWhileNVMControllerBusy(void)\r
-{\r
/* Poll the NVM STATUS register while the NVM controller is busy */\r
- for (;;)\r
+ while (TCNT0 < NVM_BUSY_TIMEOUT_MS)\r
{\r
+ /* Send a LDS command to read the NVM STATUS register to check the BUSY flag */\r
PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
NVMTarget_SendNVMRegAddress(NVM_REG_STATUS);\r
\r
+ /* Check to see if the BUSY flag is still set */\r
if (!(PDITarget_ReceiveByte() & (1 << 7)))\r
- return;\r
+ return true;\r
}\r
+ \r
+ return false;\r
}\r
\r
uint32_t NVMTarget_GetMemoryCRC(uint8_t MemoryCommand)\r
PDITarget_SendByte(1 << 0);\r
\r
/* Wait until the NVM bus and controller is no longer busy */\r
- NVMTarget_WaitWhileNVMBusBusy();\r
+ PDITarget_WaitWhileNVMBusBusy();\r
NVMTarget_WaitWhileNVMControllerBusy();\r
\r
- /* Read the three bytes generated CRC value */\r
+ /* Read the first generated CRC byte value */\r
PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
NVMTarget_SendNVMRegAddress(NVM_REG_DAT0);\r
MemoryCRC = PDITarget_ReceiveByte();\r
\r
+ /* Read the second generated CRC byte value */\r
PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
NVMTarget_SendNVMRegAddress(NVM_REG_DAT1);\r
MemoryCRC |= ((uint16_t)PDITarget_ReceiveByte() << 8);\r
\r
+ /* Read the third generated CRC byte value */\r
PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
NVMTarget_SendNVMRegAddress(NVM_REG_DAT2);\r
MemoryCRC |= ((uint32_t)PDITarget_ReceiveByte() << 16);\r
void NVMTarget_ReadMemory(uint32_t ReadAddress, uint8_t* ReadBuffer, uint16_t ReadSize)\r
{\r
NVMTarget_WaitWhileNVMControllerBusy();\r
-\r
+ \r
+ /* Send the READNVM command to the NVM controller for reading of an aribtrary location */\r
PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));\r
NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
PDITarget_SendByte(NVM_CMD_READNVM);\r
\r
- /* TODO: Optimize via REPEAT and buffer orientated commands */\r
- for (uint16_t i = 0; i < ReadSize; i++)\r
+ /* Send the address of the first location to read from - this also primes the internal address\r
+ * counters so that we can use the REPEAT command later to save on overhead for multiple bytes */\r
+ PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
+ NVMTarget_SendAddress(ReadAddress);\r
+ *(ReadBuffer++) = PDITarget_ReceiveByte();\r
+\r
+ /* Check to see if we are reading more than a single byte */\r
+ if (ReadSize > 1)\r
{\r
- PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));\r
- NVMTarget_SendAddress(ReadAddress++);\r
- *(ReadBuffer++) = PDITarget_ReceiveByte();\r
+ /* Decrement the ReadSize counter as we have already read once byte of memory */\r
+ ReadSize--;\r
+ \r
+ /* Send the REPEAT command with the specified number of bytes remaining to read */\r
+ PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_2BYTES);\r
+ PDITarget_SendByte(ReadSize & 0xFF);\r
+ PDITarget_SendByte(ReadSize >> 8);\r
+ \r
+ /* Send a LD command with indirect access and postincrement to read out the remaining bytes */\r
+ PDITarget_SendByte(PDI_CMD_LD | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);\r
+ for (uint16_t i = 1; i < ReadSize; i++)\r
+ *(ReadBuffer++) = PDITarget_ReceiveByte();\r
}\r
}\r
\r
NVMTarget_SendNVMRegAddress(NVM_REG_CMD);\r
PDITarget_SendByte(EraseCommand);\r
\r
+ /* Chip erase is handled seperately, since it's procedure is different to other erase types */\r
if (EraseCommand == NVM_CMD_CHIPERASE)\r
{\r
/* Set CMDEX bit in NVM CTRLA register to start the chip erase */\r
PDITarget_SendByte(0x00);\r
}\r
\r
- NVMTarget_WaitWhileNVMBusBusy();\r
+ /* Wait until both the NVM bus and NVM controller are ready again */\r
+ PDITarget_WaitWhileNVMBusBusy();\r
NVMTarget_WaitWhileNVMControllerBusy();\r
}\r
\r
projects / pub / USBasp.git / blobdiff