PDITarget_EnableTargetPDI();\r
\r
/* Store the RESET key into the RESET PDI register to keep the XMEGA in reset */\r
- PDITarget_SendByte(PDI_CMD_STCS | PD_RESET_REG); \r
+ PDITarget_SendByte(PDI_CMD_STCS | PDI_RESET_REG); \r
PDITarget_SendByte(PDI_RESET_KEY);\r
\r
/* Enable access to the XPROG NVM bus by sending the documented NVM access key to the device */\r
for (uint8_t i = sizeof(PDI_NVMENABLE_KEY); i > 0; i--)\r
PDITarget_SendByte(PDI_NVMENABLE_KEY[i - 1]);\r
\r
- /* Poll the STATUS register to check to see if NVM access has been enabled */\r
- uint8_t NVMAttemptsRemaining = 255;\r
- while (NVMAttemptsRemaining)\r
- {\r
- PDITarget_SendByte(PDI_CMD_LDCS | PD_STATUS_REG);\r
- if (PDITarget_ReceiveByte() & PDI_STATUS_NVM)\r
- break;\r
-\r
- NVMAttemptsRemaining--;\r
- }\r
+ /* Wait until the NVM bus becomes active */\r
+ bool NVMBusEnabled = PDITarget_WaitWhileNVMBusBusy();\r
\r
Endpoint_Write_Byte(CMD_XPROG);\r
Endpoint_Write_Byte(XPRG_CMD_ENTER_PROGMODE);\r
- Endpoint_Write_Byte(NVMAttemptsRemaining ? XPRG_ERR_OK : XPRG_ERR_FAILED);\r
+ Endpoint_Write_Byte(NVMBusEnabled ? XPRG_ERR_OK : XPRG_ERR_FAILED);\r
Endpoint_ClearIN();\r
}\r
\r
Endpoint_SetEndpointDirection(ENDPOINT_DIR_IN);\r
\r
/* Clear the RESET key into the RESET PDI register to allow the XMEGA to run */\r
- PDITarget_SendByte(PDI_CMD_STCS | PD_RESET_REG); \r
+ PDITarget_SendByte(PDI_CMD_STCS | PDI_RESET_REG); \r
PDITarget_SendByte(0x00);\r
\r
PDITarget_DisableTargetPDI();\r