Fixed compilation error in the AudioInput demos when MICROPHONE_BIASED_TO_HALF_RAIL...

[pub/USBasp.git] / Projects / AVRISP-MKII / Lib / XPROG / XPROGTarget.c

diff --git a/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c b/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c
index 3a74e15..bfc2e82 100644 (file)
--- a/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c
+++ b/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c
@@ -80,10 +80,6 @@ ISR(TIMER1_COMPA_vect, ISR_BLOCK)
        }\r
        else\r
        {\r
        }\r
        else\r
        {\r

-               /* If not sending or receiving, just exit */\r
-               if (!(SoftUSART_BitCount))\r
-                 return;\r
-\r

                /* If at falling clock edge and we are in receive mode, abort */\r
                if (!IsSending)\r
                  return;\r
                /* If at falling clock edge and we are in receive mode, abort */\r
                if (!IsSending)\r
                  return;\r


@@ -162,7 +158,7 @@ void XPROGTarget_EnableTargetPDI(void)
        \r
        /* Set up the synchronous USART for XMEGA communications - \r
           8 data bits, even parity, 2 stop bits */\r
        \r
        /* Set up the synchronous USART for XMEGA communications - \r
           8 data bits, even parity, 2 stop bits */\r

-       UBRR1  = (F_CPU / 500000UL);\r
+       UBRR1  = (F_CPU / XPROG_HARDWARE_SPEED);\r

        UCSR1B = (1 << TXEN1);\r
        UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);\r
 #else\r
        UCSR1B = (1 << TXEN1);\r
        UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);\r
 #else\r


@@ -203,7 +199,7 @@ void XPROGTarget_EnableTargetTPI(void)
                \r
        /* Set up the synchronous USART for TINY communications - \r
           8 data bits, even parity, 2 stop bits */\r
                \r
        /* Set up the synchronous USART for TINY communications - \r
           8 data bits, even parity, 2 stop bits */\r

-       UBRR1  = (F_CPU / 500000UL);\r
+       UBRR1  = (F_CPU / XPROG_HARDWARE_SPEED);\r

        UCSR1B = (1 << TXEN1);\r
        UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);\r
 #else\r
        UCSR1B = (1 << TXEN1);\r
        UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);\r
 #else\r


@@ -239,16 +235,18 @@ void XPROGTarget_DisableTargetPDI(void)
 \r
        /* Tristate all pins */\r
        DDRD  &= ~((1 << 5) | (1 << 3));\r
 \r
        /* Tristate all pins */\r
        DDRD  &= ~((1 << 5) | (1 << 3));\r

-       PORTD &= ~((1 << 3) | (1 << 2));\r
+       PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));\r

 #else\r
        /* Turn off software USART management timer */\r
        TCCR1B = 0;\r
 \r
 #else\r
        /* Turn off software USART management timer */\r
        TCCR1B = 0;\r
 \r

-       /* Tristate all pins */\r
+       /* Set DATA and CLOCK lines to inputs */\r

        BITBANG_PDIDATA_DDR   &= ~BITBANG_PDIDATA_MASK;\r
        BITBANG_PDICLOCK_DDR  &= ~BITBANG_PDICLOCK_MASK;\r
        BITBANG_PDIDATA_DDR   &= ~BITBANG_PDIDATA_MASK;\r
        BITBANG_PDICLOCK_DDR  &= ~BITBANG_PDICLOCK_MASK;\r

-       BITBANG_PDICLOCK_PORT &= ~BITBANG_PDICLOCK_MASK;        \r
+       \r
+       /* Tristate DATA and CLOCK lines */\r

        BITBANG_PDIDATA_PORT  &= ~BITBANG_PDIDATA_MASK;\r
        BITBANG_PDIDATA_PORT  &= ~BITBANG_PDIDATA_MASK;\r

+       BITBANG_PDICLOCK_PORT &= ~BITBANG_PDICLOCK_MASK;        \r

 #endif\r
 }\r
 \r
 #endif\r
 }\r
 \r