Fix NVM commands so that memory reads and CRC generations now work correctly using...

[pub/USBasp.git] / Projects / AVRISP / Lib / NVMTarget.h

diff --git a/Projects/AVRISP/Lib/NVMTarget.h b/Projects/AVRISP/Lib/NVMTarget.h
index 5afb4c0..0f2dad5 100644 (file)
--- a/Projects/AVRISP/Lib/NVMTarget.h
+++ b/Projects/AVRISP/Lib/NVMTarget.h
@@ -56,35 +56,66 @@
                #endif\r
 \r
        /* Defines: */\r
-               #define FLASH_BASE           0x00800000\r
-               #define EPPROM_BASE          0x008C0000\r
-               #define FUSE_BASE            0x008F0020\r
-               #define DATAMEM_BASE         0x01000000\r
-               #define PROD_SIGNATURE_BASE  0x008E0200\r
-               #define USER_SIGNATURE_BASE  0x008E0400\r
+               #define FLASH_BASE                     0x00800000\r
+               #define EPPROM_BASE                    0x008C0000\r
+               #define FUSE_BASE                      0x008F0020\r
+               #define DATAMEM_BASE                   0x01000000\r
+               #define PROD_SIGNATURE_BASE            0x008E0200\r
+               #define USER_SIGNATURE_BASE            0x008E0400\r
                \r
-               #define NVM_REG_ADDR0        0x00\r
-               #define NVM_REG_ADDR1        0x01\r
-               #define NVM_REG_ADDR2        0x02\r
-               #define NVM_REG_DAT0         0x04\r
-               #define NVM_REG_DAT1         0x05\r
-               #define NVM_REG_DAT2         0x06\r
-               #define NVM_REG_CMD          0x0A\r
-               #define NVM_REG_CTRLA        0x0B\r
-               #define NVM_REG_CTRLB        0x0C\r
-               #define NVM_REG_INTCTRL      0x0D\r
-               #define NVM_REG_STATUS       0x0F\r
-               #define NVM_REG_LOCKBITS     0x10\r
+               #define NVM_REG_ADDR0                  0x00\r
+               #define NVM_REG_ADDR1                  0x01\r
+               #define NVM_REG_ADDR2                  0x02\r
+               #define NVM_REG_DAT0                   0x04\r
+               #define NVM_REG_DAT1                   0x05\r
+               #define NVM_REG_DAT2                   0x06\r
+               #define NVM_REG_CMD                    0x0A\r
+               #define NVM_REG_CTRLA                  0x0B\r
+               #define NVM_REG_CTRLB                  0x0C\r
+               #define NVM_REG_INTCTRL                0x0D\r
+               #define NVM_REG_STATUS                 0x0F\r
+               #define NVM_REG_LOCKBITS               0x10\r
                \r
-               #define NVM_CMD_APPCRC       0x38\r
-               #define NVM_CMD_BOOTCRC      0x39\r
-               #define NVM_CMD_FLASHCRC     0x78\r
-               #define NVM_CMD_READUSERSIG  0x03\r
-                               \r
+               #define NVM_CMD_NOOP                   0x00\r
+               #define NVM_CMD_CHIPERASE              0x40\r
+               #define NVM_CMD_READNVM                0x43\r
+               #define NVM_CMD_LOADFLASHBUFF          0x23\r
+               #define NVM_CMD_ERASEFLASHBUFF         0x26\r
+               #define NVM_CMD_ERASEFLASHPAGE         0x2B\r
+               #define NVM_CMD_FLASHPAGEWRITE         0x2E\r
+               #define NVM_CMD_ERASEWRITEFLASH        0x2F\r
+               #define NVM_CMD_FLASHCRC               0x78\r
+               #define NVM_CMD_ERASEAPPSEC            0x20\r
+               #define NVM_CMD_ERASEAPPSECPAGE        0x22\r
+               #define NVM_CMD_WRITEAPPSECPAGE        0x24\r
+               #define NVM_CMD_ERASEWRITEAPPSECPAGE   0x25\r
+               #define NVM_CMD_APPCRC                 0x38\r
+               #define NVM_CMD_ERASEBOOTSEC           0x68\r
+               #define NVM_CMD_ERASEBOOTSECPAGE       0x2A\r
+               #define NVM_CMD_WRITEBOOTSECPAGE       0x2C\r
+               #define NVM_CMD_ERASEWRITEBOOTSECPAGE  0x2D\r
+               #define NVM_CMD_BOOTCRC                0x39\r
+               #define NVM_CMD_READUSERSIG            0x03\r
+               #define NVM_CMD_ERASEUSERSIG           0x18\r
+               #define NVM_CMD_WRITEUSERSIG           0x1A\r
+               #define NVM_CMD_READCALIBRATION        0x02\r
+               #define NVM_CMD_READFUSE               0x07\r
+               #define NVM_CMD_WRITEFUSE              0x4C\r
+               #define NVM_CMD_WRITELOCK              0x08\r
+               #define NVM_CMD_LOADEEPROMPAGEBUFF     0x33\r
+               #define NVM_CMD_ERASEEEPROMPAGEBUFF    0x36\r
+               #define NVM_CMD_ERASEEEPROM            0x30\r
+               #define NVM_CMD_ERASEEEPROMPAGE        0x32\r
+               #define NVM_CMD_WRITEEEPROMPAGE        0x34\r
+               #define NVM_CMD_ERASEWRITEEEPROMPAGE   0x35\r
+               #define NVM_CMD_READEEPROM             0x06\r
+\r
        /* Function Prototypes: */\r
-               void NVMTarget_SendNVMRegAddress(uint8_t Register);\r
+               void     NVMTarget_SendNVMRegAddress(uint8_t Register);\r
+               void     NVMTarget_SendAddress(uint32_t AbsoluteAddress);\r
                bool     NVMTarget_WaitWhileNVMBusBusy(void);\r
                void     NVMTarget_WaitWhileNVMControllerBusy(void);\r
                uint32_t NVMTarget_GetMemoryCRC(uint8_t MemoryCommand);\r
+               void     NVMTarget_ReadMemory(uint32_t ReadAddress, uint8_t* ReadBuffer, uint16_t ReadSize);\r
 \r
 #endif\r