Ooops - TeensyHID bootloader makefile should use a 16MHz FCPU, not 8MHz.

[pub/USBasp.git] / Projects / AVRISP / AVRISP.txt

diff --git a/Projects/AVRISP/AVRISP.txt b/Projects/AVRISP/AVRISP.txt
index fcb0fdd..35cf937 100644 (file)
--- a/Projects/AVRISP/AVRISP.txt
+++ b/Projects/AVRISP/AVRISP.txt
@@ -6,18 +6,18 @@
  \r
 /** \mainpage AVRISP MKII Programmer Project\r
  *\r
  \r
 /** \mainpage AVRISP MKII Programmer Project\r
  *\r

- *  \section SSec_Compat Demo Compatibility:\r
+ *  \section SSec_Compat Project Compatibility:\r

  *\r
  *\r

- *  The following list indicates what microcontrollers are compatible with this demo.\r
+ *  The following list indicates what microcontrollers are compatible with this project.\r

  *\r
  *  - Series 7 USB AVRs\r
  *  - Series 6 USB AVRs\r
  *  - Series 4 USB AVRs\r
  *\r
  *  - Series 7 USB AVRs\r
  *  - Series 6 USB AVRs\r
  *  - Series 4 USB AVRs\r

- *  - Series 2 USB AVRs\r
+ *  - Series 2 USB AVRs (8KB versions with reduced features only)\r

  *\r
  *  \section SSec_Info USB Information:\r
  *\r
  *\r
  *  \section SSec_Info USB Information:\r
  *\r

- *  The following table gives a rundown of the USB utilization of this demo.\r
+ *  The following table gives a rundown of the USB utilization of this project.\r

  *\r
  * <table>\r
  *  <tr>\r
  *\r
  * <table>\r
  *  <tr>\r


@@ -51,18 +51,24 @@
  *  level conversion can be made to allow for the programming of 3.3V AVR designs.\r
  *\r
  *  This device spoofs Atmel's official AVRISP-MKII device PID so that it remains compatible with Atmel's AVRISP-MKII\r
  *  level conversion can be made to allow for the programming of 3.3V AVR designs.\r
  *\r
  *  This device spoofs Atmel's official AVRISP-MKII device PID so that it remains compatible with Atmel's AVRISP-MKII\r

- *  drivers. When promted, direct your OS to install Atmel's AVRISP-MKII drivers provided with AVRStudio.\r
+ *  drivers. When prompted, direct your OS to install Atmel's AVRISP-MKII drivers provided with AVRStudio.\r

  *\r
  *  Note that this design currently has several limitations:\r
  *\r
  *  Note that this design currently has several limitations:\r

- *    - Minimum target clock speed of 500KHz due to hardware SPI used\r
+ *    - Minimum ISP target clock speed of 500KHz due to hardware SPI used\r

  *    - No reversed/shorted target connector detection and notification\r
  *    - No reversed/shorted target connector detection and notification\r

- *    - PDI programming is not supported for XMEGA targets\r

  *\r
  *\r

- *  On AVR models with an ADC converter, ACC should be tied to 5V (e.g. VBUS) and the VTARGET_ADC_CHANNEL token should be\r
+ *  On AVR models with an ADC converter, AVCC should be tied to 5V (e.g. VBUS) and the VTARGET_ADC_CHANNEL token should be\r

  *  set to an appropriate ADC channel number in the project makefile for VTARGET detection to operate correctly. On models\r
  *  without an ADC converter, VTARGET will report at a fixed 5V level.\r
  *\r
  *  set to an appropriate ADC channel number in the project makefile for VTARGET detection to operate correctly. On models\r
  *  without an ADC converter, VTARGET will report at a fixed 5V level.\r
  *\r

- *  Connections to the device are simple:\r
+ *  When compiled for the XPLAIN board target, this will automatically configure itself for the correct connections to the\r
+ *  XPLAIN's XMEGA AVR, and will enable PDI only programming support (since ISP mode is not needed).\r
+ *\r
+ *  While this application can be compiled for USB AVRs with as little as 8KB of FLASH, for full functionality 16KB or more\r
+ *  of FLASH is required. On 8KB devices, either ISP or PDI programming support can be disabled to reduce program size.\r
+ *\r
+ *  \section Sec_ISP ISP Connections\r
+ *  Connections to the device for SPI programming (when enabled):\r

  *\r
  *  <table>\r
  *   <tr>\r
  *\r
  *  <table>\r
  *   <tr>\r


@@ -105,9 +111,53 @@
  *  <b><sup>1</sup></b> <i>Optional, see \ref SSec_Options section - for USB AVRs with ADC modules only</i> \n\r
  *  <b><sup>2</sup></b> <i>See \ref SSec_Options section</i>\r
  *\r
  *  <b><sup>1</sup></b> <i>Optional, see \ref SSec_Options section - for USB AVRs with ADC modules only</i> \n\r
  *  <b><sup>2</sup></b> <i>See \ref SSec_Options section</i>\r
  *\r

+ *  \section Sec_PDI PDI Connections\r
+ *  Connections to the device for PDI programming<b><sup>1</sup></b> (when enabled):\r
+ *\r
+ *  <table>\r
+ *   <tr>\r
+ *    <td><b>Programmer Pin:</b></td>\r
+ *    <td><b>Target Device Pin:</b></td>\r
+ *    <td><b>PDI 6 Pin Layout:</b></td>\r
+ *   </tr>\r
+ *   <tr>\r
+ *    <td>MISO</td>\r
+ *    <td>DATA</td>\r
+ *    <td>1</td>\r
+ *   </tr>\r
+ *   <tr>\r
+ *    <td>ADCx <b><sup>1</sup></b></td>\r
+ *    <td>VTARGET</td>\r
+ *    <td>2</td>\r
+ *   </tr>\r
+ *   <tr>\r
+ *    <td>N/A</td>\r
+ *    <td>N/A</td>\r
+ *    <td>3</td>\r
+ *   </tr>\r
+ *   <tr>\r
+ *    <td>N/A</td>\r
+ *    <td>N/A</td>\r
+ *    <td>4</td>\r
+ *   </tr>\r
+ *   <tr>\r
+ *    <td>PORTx.y <b><sup>2</sup></b></td>\r
+ *    <td>CLOCK</td>\r
+ *    <td>5</td>\r
+ *   </tr>\r
+ *   <tr>\r
+ *    <td>GND</td>\r
+ *    <td>GND</td>\r
+ *    <td>6</td>\r
+ *   </tr>\r
+ *  </table>\r
+ *\r
+ *  <b><sup>1</sup></b> <i>When PDI_VIA_HARDWARE_USART is set, the AVR's Tx and Rx become the DATA line when connected together\r
+ *                         via a pair of 300 ohm resistors, and the AVR's XCK pin becomes CLOCK.</i>\r
+ *\r

  *  \section SSec_Options Project Options\r
  *\r
  *  \section SSec_Options Project Options\r
  *\r

- *  The following defines can be found in this demo, which can control the demo behaviour when defined, or changed in value.\r
+ *  The following defines can be found in this project, which can control the project behaviour when defined, or changed in value.\r

  *\r
  *  <table>\r
  *   <tr>\r
  *\r
  *  <table>\r
  *   <tr>\r


@@ -118,24 +168,48 @@
  *   <tr>\r
  *    <td>RESET_LINE_PORT</td>\r
  *    <td>Makefile CDEFS</td>\r
  *   <tr>\r
  *    <td>RESET_LINE_PORT</td>\r
  *    <td>Makefile CDEFS</td>\r

- *    <td>PORT register for the programmer's target RESET line.</td>\r
+ *    <td>PORT register for the programmer's target RESET line. <i>Ignored when compiled for the XPLAIN board.</i></td>\r
+ *   </tr>\r
+ *   <tr>\r
+ *    <td>RESET_LINE_PIN</td>\r
+ *    <td>Makefile CDEFS</td>\r
+ *    <td>PIN register for the programmer's target RESET line. <i>Ignored when compiled for the XPLAIN board.</i></td>\r

  *   </tr>\r
  *   <tr>\r
  *    <td>RESET_LINE_DDR</td>\r
  *    <td>Makefile CDEFS</td>\r
  *   </tr>\r
  *   <tr>\r
  *    <td>RESET_LINE_DDR</td>\r
  *    <td>Makefile CDEFS</td>\r

- *    <td>DDR register for the programmer's target RESET line.</td>\r
+ *    <td>DDR register for the programmer's target RESET line. <i>Ignored when compiled for the XPLAIN board.</i></td>\r

  *   </tr>\r
  *   <tr>\r
  *    <td>RESET_LINE_MASK</td>\r
  *    <td>Makefile CDEFS</td>\r
  *    <td>Mask for the programmer's target RESET line on the chosen port. <b>Must not be the AVR's /SS pin</b>, as the\r
  *        target pins are tri-stated when not in use, and low signals on the /SS pin will force SPI slave mode when the\r
  *   </tr>\r
  *   <tr>\r
  *    <td>RESET_LINE_MASK</td>\r
  *    <td>Makefile CDEFS</td>\r
  *    <td>Mask for the programmer's target RESET line on the chosen port. <b>Must not be the AVR's /SS pin</b>, as the\r
  *        target pins are tri-stated when not in use, and low signals on the /SS pin will force SPI slave mode when the\r

- *        pin is configured as an input.</td>\r
+ *        pin is configured as an input. When in PDI programming mode, this is the target clock pin.\r
+ *        <i>Ignored when compiled for the XPLAIN board.</i></td>\r

  *   </tr>\r
  *   <tr>\r
  *    <td>VTARGET_ADC_CHANNEL</td>\r
  *    <td>Makefile CDEFS</td>\r
  *    <td>ADC channel number (on supported AVRs) to use for VTARGET level detection.</td> \r
  *   </tr>\r
  *   </tr>\r
  *   <tr>\r
  *    <td>VTARGET_ADC_CHANNEL</td>\r
  *    <td>Makefile CDEFS</td>\r
  *    <td>ADC channel number (on supported AVRs) to use for VTARGET level detection.</td> \r
  *   </tr>\r

+ *   <tr>\r
+ *    <td>ENABLE_ISP_PROTOCOL</td>\r
+ *    <td>Makefile CDEFS</td>\r
+ *    <td>Define to enable SPI programming protocol support. <i>Ignored when compiled for the XPLAIN board.</i></td>  \r
+ *   </tr>\r
+ *   <tr>\r
+ *    <td>ENABLE_PDI_PROTOCOL</td>\r
+ *    <td>Makefile CDEFS</td>\r
+ *    <td>Define to enable XMEGA PDI programming protocol support. <i>Ignored when compiled for the XPLAIN board.</i></td>  \r
+ *   </tr>\r
+ *   <tr>\r
+ *    <td>PDI_VIA_HARDWARE_USART</td>\r
+ *    <td>Makefile CDEFS</td>\r
+ *    <td>Define to force the PDI protocol (when enabled) to use the much faster hardware USART instead of bit-banging to\r
+ *        match the official AVRISP pinout. This breaks pinout compatibility with the official AVRISP MKII (and requires \r
+ *        seperate ISP and PDI programming headers) but increases programming speed dramatically.\r
+ *        <i>Ignored when compiled for the XPLAIN board.</i></td>  \r
+ *   </tr>\r

  *  </table>\r
  */\r
  *  </table>\r
  */\r