}\r
\r
/** ISR to manage the TPI software USART when bit-banged TPI USART mode is selected. */\r
-ISR(TIMER1_COMPB_vect, ISR_BLOCK)\r
+ISR(TIMER1_CAPT_vect, ISR_BLOCK)\r
{\r
/* Toggle CLOCK pin in a single cycle (see AVR datasheet) */\r
BITBANG_TPICLOCK_PIN |= BITBANG_TPICLOCK_MASK;\r
\r
/* Set DATA line high for at least 90ns to disable /RESET functionality */\r
PORTD |= (1 << 3);\r
- _delay_ms(1);\r
+ _delay_us(1);\r
\r
/* Set up the synchronous USART for XMEGA communications - \r
8 data bits, even parity, 2 stop bits */\r
\r
/* Set DATA line high for at least 90ns to disable /RESET functionality */\r
BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;\r
- _delay_ms(1);\r
+ _delay_us(1);\r
\r
/* Fire timer compare channel A ISR to manage the software USART */\r
OCR1A = BITS_BETWEEN_USART_CLOCKS;\r
/* Set /RESET line low for at least 400ns to enable TPI functionality */\r
AUX_LINE_DDR |= AUX_LINE_MASK;\r
AUX_LINE_PORT &= ~AUX_LINE_MASK;\r
- _delay_ms(1);\r
+ _delay_us(1);\r
\r
#if defined(XPROG_VIA_HARDWARE_USART)\r
/* Set Tx and XCK as outputs, Rx as input */\r
/* Set DATA line high for idle state */\r
BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;\r
\r
- /* Fire timer capture channel B ISR to manage the software USART */\r
- OCR1B = BITS_BETWEEN_USART_CLOCKS;\r
- TCCR1B = (1 << WGM12) | (1 << CS10);\r
- TIMSK1 = (1 << OCIE1B);\r
+ /* Fire timer capture channel ISR to manage the software USART */\r
+ ICR1 = BITS_BETWEEN_USART_CLOCKS;\r
+ TCCR1B = (1 << WGM13) | (1 << WGM12) | (1 << CS10);\r
+ TIMSK1 = (1 << ICIE1);\r
#endif\r
\r
/* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */\r