Oops - PDI handshake delay was too long, causing the device's /RESET functionality...

[pub/USBasp.git] / Projects / AVRISP-MKII / Lib / XPROG / XPROGTarget.c

diff --git a/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c b/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c
index 1406428..843bf5a 100644 (file)
--- a/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c
+++ b/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c
@@ -96,7 +96,7 @@ ISR(TIMER1_COMPA_vect, ISR_BLOCK)
 }\r
 \r
 /** ISR to manage the TPI software USART when bit-banged TPI USART mode is selected. */\r
 }\r
 \r
 /** ISR to manage the TPI software USART when bit-banged TPI USART mode is selected. */\r

-ISR(TIMER1_COMPB_vect, ISR_BLOCK)\r
+ISR(TIMER1_CAPT_vect, ISR_BLOCK)\r

 {\r
        /* Toggle CLOCK pin in a single cycle (see AVR datasheet) */\r
        BITBANG_TPICLOCK_PIN |= BITBANG_TPICLOCK_MASK;\r
 {\r
        /* Toggle CLOCK pin in a single cycle (see AVR datasheet) */\r
        BITBANG_TPICLOCK_PIN |= BITBANG_TPICLOCK_MASK;\r


@@ -152,9 +152,11 @@ void XPROGTarget_EnableTargetPDI(void)
        DDRD |=  (1 << 5) | (1 << 3);\r
        DDRD &= ~(1 << 2);\r
        \r
        DDRD |=  (1 << 5) | (1 << 3);\r
        DDRD &= ~(1 << 2);\r
        \r

-       /* Set DATA line high for at least 90ns to disable /RESET functionality */\r
+       /* Set DATA line high for at least 90ns to disable /RESET functionality (note: too long will enable it again,\r
+        * so a fixed number of NOPs are used here */\r

        PORTD |= (1 << 3);\r
        PORTD |= (1 << 3);\r

-       _delay_ms(1);\r
+       asm volatile ("NOP"::);\r
+       asm volatile ("NOP"::);\r

        \r
        /* Set up the synchronous USART for XMEGA communications - \r
           8 data bits, even parity, 2 stop bits */\r
        \r
        /* Set up the synchronous USART for XMEGA communications - \r
           8 data bits, even parity, 2 stop bits */\r


@@ -166,9 +168,11 @@ void XPROGTarget_EnableTargetPDI(void)
        BITBANG_PDIDATA_DDR  |= BITBANG_PDIDATA_MASK;\r
        BITBANG_PDICLOCK_DDR |= BITBANG_PDICLOCK_MASK;\r
        \r
        BITBANG_PDIDATA_DDR  |= BITBANG_PDIDATA_MASK;\r
        BITBANG_PDICLOCK_DDR |= BITBANG_PDICLOCK_MASK;\r
        \r

-       /* Set DATA line high for at least 90ns to disable /RESET functionality */\r
+       /* Set DATA line high for at least 90ns to disable /RESET functionality (note: too long will enable it again,\r
+        * so a fixed number of NOPs are used here */\r

        BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;\r
        BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;\r

-       _delay_ms(1);\r
+       asm volatile ("NOP"::);\r
+       asm volatile ("NOP"::);\r

 \r
        /* Fire timer compare channel A ISR to manage the software USART */\r
        OCR1A   = BITS_BETWEEN_USART_CLOCKS;\r
 \r
        /* Fire timer compare channel A ISR to manage the software USART */\r
        OCR1A   = BITS_BETWEEN_USART_CLOCKS;\r


@@ -209,10 +213,10 @@ void XPROGTarget_EnableTargetTPI(void)
        /* Set DATA line high for idle state */\r
        BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;\r
 \r
        /* Set DATA line high for idle state */\r
        BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;\r
 \r

-       /* Fire timer capture channel B ISR to manage the software USART */\r
-       OCR1B   = BITS_BETWEEN_USART_CLOCKS;\r
-       TCCR1B  = (1 << WGM12) | (1 << CS10);\r
-       TIMSK1  = (1 << OCIE1B);\r
+       /* Fire timer capture channel ISR to manage the software USART */\r
+       ICR1    = BITS_BETWEEN_USART_CLOCKS;\r
+       TCCR1B  = (1 << WGM13) | (1 << WGM12) | (1 << CS10);\r
+       TIMSK1  = (1 << ICIE1);\r

 #endif\r
 \r
        /* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */\r
 #endif\r
 \r
        /* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */\r