Projects/AVRISP/Lib/NVMTarget.c

   1 /*
   2              LUFA Library
   3      Copyright (C) Dean Camera, 2009.
   4
   5   dean [at] fourwalledcubicle [dot] com
   6       www.fourwalledcubicle.com
   7 */
   8
   9 /*
  10   Copyright 2009  Dean Camera (dean [at] fourwalledcubicle [dot] com)
  11
  12   Permission to use, copy, modify, and distribute this software
  13   and its documentation for any purpose and without fee is hereby
  14   granted, provided that the above copyright notice appear in all
  15   copies and that both that the copyright notice and this
  16   permission notice and warranty disclaimer appear in supporting
  17   documentation, and that the name of the author not be used in
  18   advertising or publicity pertaining to distribution of the
  19   software without specific, written prior permission.
  20
  21   The author disclaim all warranties with regard to this
  22   software, including all implied warranties of merchantability
  23   and fitness.  In no event shall the author be liable for any
  24   special, indirect or consequential damages or any damages
  25   whatsoever resulting from loss of use, data or profits, whether
  26   in an action of contract, negligence or other tortious action,
  27   arising out of or in connection with the use or performance of
  28   this software.
  29 */
  30
  31 /** \file
  32  *
  33  *  Target-related functions for the target's NVM module.
  34  */
  35
  36 #define  INCLUDE_FROM_NVMTARGET_C
  37 #include "NVMTarget.h"
  38
  39 #if defined(ENABLE_PDI_PROTOCOL) || defined(__DOXYGEN__)
  40
  41 /** Sends the given NVM register address to the target.
  42  *
  43  *  \param[in] Register  NVM register whose absolute address is to be sent
  44  */
  45 void NVMTarget_SendNVMRegAddress(uint8_t Register)
  46 {
  47         /* Determine the absolute register address from the NVM base memory address and the NVM register address */
  48         uint32_t Address = XPROG_Param_NVMBase | Register;
  49
  50         /* Send the calculated 32-bit address to the target, LSB first */
  51         PDITarget_SendByte(Address &  0xFF);
  52         PDITarget_SendByte(Address >> 8);
  53         PDITarget_SendByte(Address >> 16);
  54         PDITarget_SendByte(Address >> 24);
  55 }
  56
  57 /** Sends the given 32-bit absolute address to the target.
  58  *
  59  *  \param[in] AbsoluteAddress  Absolute address to send to the target
  60  */
  61 void NVMTarget_SendAddress(uint32_t AbsoluteAddress)
  62 {
  63         /* Send the given 32-bit address to the target, LSB first */
  64         PDITarget_SendByte(AbsoluteAddress &  0xFF);
  65         PDITarget_SendByte(AbsoluteAddress >> 8);
  66         PDITarget_SendByte(AbsoluteAddress >> 16);
  67         PDITarget_SendByte(AbsoluteAddress >> 24);
  68 }
  69
  70 /** Waits while the target's NVM controller is busy performing an operation, exiting if the
  71  *  timeout period expires.
  72  *
  73  *  \return Boolean true if the NVM controller became ready within the timeout period, false otherwise
  74  */
  75 bool NVMTarget_WaitWhileNVMControllerBusy(void)
  76 {
  77         TCNT0 = 0;
  78
  79         /* Poll the NVM STATUS register while the NVM controller is busy */
  80         while (TCNT0 < NVM_BUSY_TIMEOUT_MS)
  81         {
  82                 /* Send a LDS command to read the NVM STATUS register to check the BUSY flag */
  83                 PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
  84                 NVMTarget_SendNVMRegAddress(NVM_REG_STATUS);
  85
  86                 /* Check to see if the BUSY flag is still set */
  87                 if (!(PDITarget_ReceiveByte() & (1 << 7)))
  88                   return true;
  89         }
  90
  91         return false;
  92 }
  93
  94 /** Retrieves the CRC value of the given memory space.
  95  *
  96  *  \param[in]  CRCCommand  NVM CRC command to issue to the target
  97  *  \param[out] CRCDest     CRC Destination when read from the target
  98  *
  99  *  \return Boolean true if the command sequence complete sucessfully
 100  */
 101 bool NVMTarget_GetMemoryCRC(uint8_t CRCCommand, uint32_t* CRCDest)
 102 {
 103         /* Wait until the NVM controller is no longer busy */
 104         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 105           return false;
 106
 107         /* Set the NVM command to the correct CRC read command */
 108         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 109         NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 110         PDITarget_SendByte(CRCCommand);
 111
 112         /* Set CMDEX bit in NVM CTRLA register to start the CRC generation */
 113         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 114         NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);
 115         PDITarget_SendByte(1 << 0);
 116
 117         /* Wait until the NVM bus is ready again */
 118         if (!(PDITarget_WaitWhileNVMBusBusy()))
 119           return false;
 120
 121         /* Wait until the NVM controller is no longer busy */
 122         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 123           return false;
 124
 125         *CRCDest = 0;
 126
 127         /* Read the first generated CRC byte value */
 128         PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
 129         NVMTarget_SendNVMRegAddress(NVM_REG_DAT0);
 130         *CRCDest  = PDITarget_ReceiveByte();
 131
 132         /* Read the second generated CRC byte value */
 133         PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
 134         NVMTarget_SendNVMRegAddress(NVM_REG_DAT1);
 135         *CRCDest |= ((uint16_t)PDITarget_ReceiveByte() << 8);
 136
 137         /* Read the third generated CRC byte value */
 138         PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
 139         NVMTarget_SendNVMRegAddress(NVM_REG_DAT2);
 140         *CRCDest |= ((uint32_t)PDITarget_ReceiveByte() << 16);
 141
 142         return true;
 143 }
 144
 145 /** Reads memory from the target's memory spaces.
 146  *
 147  *  \param[in]  ReadAddress  Start address to read from within the target's address space
 148  *  \param[out] ReadBuffer   Buffer to store read data into
 149  *  \param[in]  ReadSize     Number of bytes to read
 150  *
 151  *  \return Boolean true if the command sequence complete sucessfully
 152  */
 153 bool NVMTarget_ReadMemory(uint32_t ReadAddress, uint8_t* ReadBuffer, uint16_t ReadSize)
 154 {
 155         /* Wait until the NVM controller is no longer busy */
 156         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 157           return false;
 158
 159         /* Send the READNVM command to the NVM controller for reading of an aribtrary location */
 160         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 161         NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 162         PDITarget_SendByte(NVM_CMD_READNVM);
 163
 164         /* Load the PDI pointer register with the start address we want to read from */
 165         PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);
 166         NVMTarget_SendAddress(ReadAddress);
 167
 168         /* Send the REPEAT command with the specified number of bytes to read */
 169         PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_2BYTES);
 170         PDITarget_SendByte(ReadSize &  0xFF);
 171         PDITarget_SendByte(ReadSize >> 8);
 172
 173         /* Send a LD command with indirect access and postincrement to read out the bytes */
 174         PDITarget_SendByte(PDI_CMD_LD | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);
 175         for (uint16_t i = 0; i < ReadSize; i++)
 176           *(ReadBuffer++) = PDITarget_ReceiveByte();
 177
 178         return true;
 179 }
 180
 181 /** Writes byte addressed memory to the target's memory spaces.
 182  *
 183  *  \param[in]  WriteCommand  Command to send to the device to write each memory byte
 184  *  \param[in]  WriteAddress  Start address to write to within the target's address space
 185  *  \param[in]  WriteBuffer   Buffer to source data from
 186  *  \param[in]  WriteSize     Number of bytes to write
 187  *
 188  *  \return Boolean true if the command sequence complete sucessfully
 189  */
 190 bool NVMTarget_WriteByteMemory(uint8_t WriteCommand, uint32_t WriteAddress, uint8_t* WriteBuffer, uint16_t WriteSize)
 191 {
 192         for (uint16_t i = 0; i < WriteSize; i++)
 193         {
 194                 /* Wait until the NVM controller is no longer busy */
 195                 if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 196                   return false;
 197
 198                 /* Send the memory write command to the target */
 199                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 200                 NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 201                 PDITarget_SendByte(WriteCommand);
 202
 203                 /* Send each new memory byte to the memory to the target */
 204                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 205                 NVMTarget_SendAddress(WriteAddress++);
 206                 PDITarget_SendByte(*(WriteBuffer++));
 207         }
 208
 209         return true;
 210 }
 211
 212 /** Writes page addressed memory to the target's memory spaces.
 213  *
 214  *  \param[in]  WriteBuffCommand  Command to send to the device to write a byte to the memory page buffer
 215  *  \param[in]  EraseBuffCommand  Command to send to the device to erase the memory page buffer
 216  *  \param[in]  WritePageCommand  Command to send to the device to write the page buffer to the destination memory
 217  *  \param[in]  PageMode          Bitfield indicating what operations need to be executed on the specified page
 218  *  \param[in]  WriteAddress      Start address to write the page data to within the target's address space
 219  *  \param[in]  WriteBuffer       Buffer to source data from
 220  *  \param[in]  WriteSize         Number of bytes to write
 221  *
 222  *  \return Boolean true if the command sequence complete sucessfully
 223  */
 224 bool NVMTarget_WritePageMemory(uint8_t WriteBuffCommand, uint8_t EraseBuffCommand, uint8_t WritePageCommand,
 225                                uint8_t PageMode, uint32_t WriteAddress, uint8_t* WriteBuffer, uint16_t WriteSize)
 226 {
 227         if (PageMode & XPRG_PAGEMODE_ERASE)
 228         {
 229                 /* Wait until the NVM controller is no longer busy */
 230                 if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 231                   return false;
 232
 233                 /* Send the memory buffer erase command to the target */
 234                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 235                 NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 236                 PDITarget_SendByte(EraseBuffCommand);
 237
 238                 /* Set CMDEX bit in NVM CTRLA register to start the buffer erase */
 239                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 240                 NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);
 241                 PDITarget_SendByte(1 << 0);
 242         }
 243
 244         if (WriteSize)
 245         {
 246                 /* Wait until the NVM controller is no longer busy */
 247                 if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 248                   return false;
 249
 250                 /* Send the memory buffer write command to the target */
 251                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 252                 NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 253                 PDITarget_SendByte(WriteBuffCommand);
 254
 255                 /* Load the PDI pointer register with the start address we want to write to */
 256                 PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);
 257                 NVMTarget_SendAddress(WriteAddress);
 258
 259                 /* Send the REPEAT command with the specified number of bytes to write */
 260                 PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_2BYTES);
 261                 PDITarget_SendByte(WriteSize &  0xFF);
 262                 PDITarget_SendByte(WriteSize >> 8);
 263
 264                 /* Send a ST command with indirect access and postincrement to write the bytes */
 265                 PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);
 266                 for (uint16_t i = 0; i < WriteSize; i++)
 267                   PDITarget_SendByte(*(WriteBuffer++));
 268
 269                 // TEMP
 270                 PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
 271                 NVMTarget_SendNVMRegAddress(NVM_REG_STATUS);
 272                 GPIOR0 = PDITarget_ReceiveByte();
 273                 if (!(GPIOR0 & (1 << 0)))
 274                   JTAG_DEBUG_POINT();
 275                 // END TEMP
 276         }
 277
 278         if (PageMode & XPRG_PAGEMODE_WRITE)
 279         {
 280                 /* Wait until the NVM controller is no longer busy */
 281                 if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 282                   return false;
 283
 284                 /* Send the memory write command to the target */
 285                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 286                 NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 287                 PDITarget_SendByte(WritePageCommand);
 288
 289                 /* Send the address of the first page location to write the memory page */
 290                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 291                 NVMTarget_SendAddress(WriteAddress);
 292                 PDITarget_SendByte(0x00);
 293         }
 294
 295         return true;
 296 }
 297
 298 /** Erases a specific memory space of the target.
 299  *
 300  *  \param[in] EraseCommand  NVM erase command to send to the device
 301  *  \param[in] Address  Address inside the memory space to erase
 302  *
 303  *  \return Boolean true if the command sequence complete sucessfully
 304  */
 305 bool NVMTarget_EraseMemory(uint8_t EraseCommand, uint32_t Address)
 306 {
 307         /* Wait until the NVM controller is no longer busy */
 308         if (!(NVMTarget_WaitWhileNVMControllerBusy()))
 309           return false;
 310
 311         /* Send the memory erase command to the target */
 312         PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 313         NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
 314         PDITarget_SendByte(EraseCommand);
 315
 316         /* Chip erase is handled seperately, since it's procedure is different to other erase types */
 317         if (EraseCommand == NVM_CMD_CHIPERASE)
 318         {
 319                 /* Set CMDEX bit in NVM CTRLA register to start the chip erase */
 320                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 321                 NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);
 322                 PDITarget_SendByte(1 << 0);
 323         }
 324         else
 325         {
 326                 /* Other erase modes just need us to address a byte within the target memory space */
 327                 PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
 328                 NVMTarget_SendAddress(Address);
 329                 PDITarget_SendByte(0x00);
 330         }
 331
 332         /* Wait until the NVM bus is ready again */
 333         if (!(PDITarget_WaitWhileNVMBusBusy()))
 334           return false;
 335
 336         return true;
 337 }
 338
 339 #endif