0a5d477b2f9fec55b0b498bc97c559a19f109f02
[pub/USBasp.git] / LUFA / Drivers / Peripheral / XMEGA / TWI_XMEGA.h
1 /*
2 LUFA Library
3 Copyright (C) Dean Camera, 2013.
4
5 dean [at] fourwalledcubicle [dot] com
6 www.lufa-lib.org
7 */
8
9 /*
10 Copyright 2013 Dean Camera (dean [at] fourwalledcubicle [dot] com)
11
12 Permission to use, copy, modify, distribute, and sell this
13 software and its documentation for any purpose is hereby granted
14 without fee, provided that the above copyright notice appear in
15 all copies and that both that the copyright notice and this
16 permission notice and warranty disclaimer appear in supporting
17 documentation, and that the name of the author not be used in
18 advertising or publicity pertaining to distribution of the
19 software without specific, written prior permission.
20
21 The author disclaims all warranties with regard to this
22 software, including all implied warranties of merchantability
23 and fitness. In no event shall the author be liable for any
24 special, indirect or consequential damages or any damages
25 whatsoever resulting from loss of use, data or profits, whether
26 in an action of contract, negligence or other tortious action,
27 arising out of or in connection with the use or performance of
28 this software.
29 */
30
31 /** \file
32 * \brief TWI Peripheral Driver (XMEGA)
33 *
34 * On-chip TWI driver for the XMEGA Family of AVR microcontrollers.
35 *
36 * \note This file should not be included directly. It is automatically included as needed by the TWI driver
37 * dispatch header located in LUFA/Drivers/Peripheral/TWI.h.
38 */
39
40 /** \ingroup Group_TWI
41 * \defgroup Group_TWI_XMEGA TWI Peripheral Driver (XMEGA)
42 *
43 * \section Sec_TWI_XMEGA_ModDescription Module Description
44 * Master mode TWI driver for the 8-bit AVR microcontrollers which contain a hardware TWI module.
45 *
46 * \note This file should not be included directly. It is automatically included as needed by the TWI driver
47 * dispatch header located in LUFA/Drivers/Peripheral/TWI.h.
48 *
49 * \section Sec_TWI_XMEGA_ExampleUsage Example Usage
50 * The following snippet is an example of how this module may be used within a typical
51 * application.
52 *
53 * <b>Low Level API Example:</b>
54 * \code
55 * // Initialize the TWI driver before first use at 200KHz
56 * TWI_Init(&TWIC, TWI_BAUD_FROM_FREQ(200000));
57 *
58 * // Start a write session to device at device address 0xA0, internal address 0xDC with a 10ms timeout
59 * if (TWI_StartTransmission(&TWIC, 0xA0 | TWI_ADDRESS_WRITE, 10) == TWI_ERROR_NoError)
60 * {
61 * TWI_SendByte(&TWIC, 0xDC);
62 *
63 * TWI_SendByte(&TWIC, 0x01);
64 * TWI_SendByte(&TWIC, 0x02);
65 * TWI_SendByte(&TWIC, 0x03);
66 *
67 * // Must stop transmission afterwards to release the bus
68 * TWI_StopTransmission(&TWIC);
69 * }
70 *
71 * // Start a read session to device at address 0xA0, internal address 0xDC with a 10ms timeout
72 * if (TWI_StartTransmission(&TWIC, 0xA0 | TWI_ADDRESS_WRITE, 10) == TWI_ERROR_NoError)
73 * {
74 * TWI_SendByte(&TWIC, 0xDC);
75 * TWI_StopTransmission(&TWIC);
76 *
77 * if (TWI_StartTransmission(&TWIC, 0xA0 | TWI_ADDRESS_READ, 10) == TWI_ERROR_NoError)
78 * {
79 * uint8_t Byte1, Byte2, Byte3;
80 *
81 * // Read three bytes, acknowledge after the third byte is received
82 * TWI_ReceiveByte(&TWIC, &Byte1, false);
83 * TWI_ReceiveByte(&TWIC, &Byte2, false);
84 * TWI_ReceiveByte(&TWIC, &Byte3, true);
85 *
86 * // Must stop transmission afterwards to release the bus
87 * TWI_StopTransmission(&TWIC);
88 * }
89 * }
90 * \endcode
91 *
92 * <b>High Level API Example:</b>
93 * \code
94 * // Initialize the TWI driver before first use at 200KHz
95 * TWI_Init(&TWIC, TWI_BAUD_FROM_FREQ(200000));
96 *
97 * // Start a write session to device at device address 0xA0, internal address 0xDC with a 10ms timeout
98 * uint8_t InternalWriteAddress = 0xDC;
99 * uint8_t WritePacket[3] = {0x01, 0x02, 0x03};
100 *
101 * TWI_WritePacket(&TWIC, 0xA0, 10, &InternalWriteAddress, sizeof(InternalWriteAddress),
102 * &WritePacket, sizeof(WritePacket);
103 *
104 * // Start a read session to device at address 0xA0, internal address 0xDC with a 10ms timeout
105 * uint8_t InternalReadAddress = 0xDC;
106 * uint8_t ReadPacket[3];
107 *
108 * TWI_ReadPacket(&TWIC, 0xA0, 10, &InternalReadAddress, sizeof(InternalReadAddress),
109 * &ReadPacket, sizeof(ReadPacket);
110 * \endcode
111 *
112 * @{
113 */
114
115 #ifndef __TWI_XMEGA_H__
116 #define __TWI_XMEGA_H__
117
118 /* Includes: */
119 #include "../../../Common/Common.h"
120
121 #include <stdio.h>
122
123 /* Enable C linkage for C++ Compilers: */
124 #if defined(__cplusplus)
125 extern "C" {
126 #endif
127
128 /* Preprocessor Checks: */
129 #if !defined(__INCLUDE_FROM_TWI_H) && !defined(__INCLUDE_FROM_TWI_C)
130 #error Do not include this file directly. Include LUFA/Drivers/Peripheral/TWI.h instead.
131 #endif
132
133 /* Public Interface - May be used in end-application: */
134 /* Macros: */
135 /** TWI slave device address mask for a read session. Mask with a slave device base address to obtain
136 * the correct TWI bus address for the slave device when reading data from it.
137 */
138 #define TWI_ADDRESS_READ 0x01
139
140 /** TWI slave device address mask for a write session. Mask with a slave device base address to obtain
141 * the correct TWI bus address for the slave device when writing data to it.
142 */
143 #define TWI_ADDRESS_WRITE 0x00
144
145 /** Mask to retrieve the base address for a TWI device, which can then be ORed with \ref TWI_ADDRESS_READ
146 * or \ref TWI_ADDRESS_WRITE to obtain the device's read and write address respectively.
147 */
148 #define TWI_DEVICE_ADDRESS_MASK 0xFE
149
150 /** Calculates the length of each bit on the TWI bus for a given target frequency. This may be used with
151 * the \ref TWI_Init() function to convert a bus frequency to a number of clocks for the \c BitLength
152 * parameter.
153 *
154 * \param[in] Frequency Desired TWI bus frequency in Hz.
155 *
156 * \return Bit length in clocks for the given TWI bus frequency at the given prescaler value.
157 */
158 #define TWI_BAUD_FROM_FREQ(Frequency) ((F_CPU / (2 * Frequency)) - 5)
159
160 /* Enums: */
161 /** Enum for the possible return codes of the TWI transfer start routine and other dependant TWI functions. */
162 enum TWI_ErrorCodes_t
163 {
164 TWI_ERROR_NoError = 0, /**< Indicates that the command completed successfully. */
165 TWI_ERROR_BusFault = 1, /**< A TWI bus fault occurred while attempting to capture the bus. */
166 TWI_ERROR_BusCaptureTimeout = 2, /**< A timeout occurred whilst waiting for the bus to be ready. */
167 TWI_ERROR_SlaveResponseTimeout = 3, /**< No ACK received at the nominated slave address within the timeout period. */
168 TWI_ERROR_SlaveNotReady = 4, /**< Slave NAKed the TWI bus START condition. */
169 TWI_ERROR_SlaveNAK = 5, /**< Slave NAKed whilst attempting to send data to the device. */
170 };
171
172 /* Inline Functions: */
173 /** Initializes the TWI hardware into master mode, ready for data transmission and reception. This must be
174 * before any other TWI operations.
175 *
176 * The generated SCL frequency will be according to the formula <pre>F_CPU / (2 * (5 + (BAUD)))</pre>.
177 *
178 * \attention The value of the \c BitLength parameter should not be set below 10 or invalid bus conditions may
179 * occur, as indicated in the XMEGA microcontroller datasheet.
180 *
181 * \param[in] twi The TWI Peripheral to use
182 * \param[in] Baud Value of the BAUD register of the TWI Master.
183 */
184 static inline void TWI_Init(TWI_t *twi, const uint8_t Baud) ATTR_ALWAYS_INLINE ATTR_NON_NULL_PTR_ARG(1);
185 static inline void TWI_Init(TWI_t *twi, const uint8_t Baud)
186 {
187 twi->CTRL = 0x00;
188 twi->MASTER.BAUD = Baud;
189 twi->MASTER.CTRLA = TWI_MASTER_ENABLE_bm;
190 twi->MASTER.CTRLB = 0;
191 twi->MASTER.STATUS = TWI_MASTER_BUSSTATE_IDLE_gc;
192 }
193
194 /** Turns off the TWI driver hardware. If this is called, any further TWI operations will require a call to
195 * \ref TWI_Init() before the TWI can be used again.
196 *
197 * \param[in] twi The TWI Peripheral to use
198 */
199 static inline void TWI_Disable(TWI_t *twi) ATTR_ALWAYS_INLINE ATTR_NON_NULL_PTR_ARG(1);
200 static inline void TWI_Disable(TWI_t *twi)
201 {
202 twi->MASTER.CTRLA &= ~TWI_MASTER_ENABLE_bm;
203 }
204
205 /** Sends a TWI STOP onto the TWI bus, terminating communication with the currently addressed device.
206 *
207 * \param[in] twi The TWI Peripheral to use
208 */
209 static inline void TWI_StopTransmission(TWI_t *twi) ATTR_ALWAYS_INLINE ATTR_NON_NULL_PTR_ARG(1);
210 static inline void TWI_StopTransmission(TWI_t *twi)
211 {
212 twi->MASTER.CTRLC = TWI_MASTER_ACKACT_bm | TWI_MASTER_CMD_STOP_gc;
213 }
214
215 /* Function Prototypes: */
216 /** Begins a master mode TWI bus communication with the given slave device address.
217 *
218 * \param[in] twi The TWI Peripheral to use
219 * \param[in] SlaveAddress Address of the slave TWI device to communicate with.
220 * \param[in] TimeoutMS Timeout period within which the slave must respond, in milliseconds.
221 *
222 * \return A value from the \ref TWI_ErrorCodes_t enum.
223 */
224 uint8_t TWI_StartTransmission(TWI_t *twi,
225 const uint8_t SlaveAddress,
226 const uint8_t TimeoutMS) ATTR_NON_NULL_PTR_ARG(1);
227
228 /** Sends a byte to the currently addressed device on the TWI bus.
229 *
230 * \param[in] twi The TWI Peripheral to use
231 * \param[in] Byte Byte to send to the currently addressed device
232 *
233 * \return Boolean \c true if the recipient ACKed the byte, \c false otherwise
234 */
235 bool TWI_SendByte(TWI_t *twi, const uint8_t Byte) ATTR_NON_NULL_PTR_ARG(1);
236
237 /** Receives a byte from the currently addressed device on the TWI bus.
238 *
239 * \param[in] twi The TWI Peripheral to use
240 * \param[in] Byte Location where the read byte is to be stored.
241 * \param[in] LastByte Indicates if the byte should be ACKed if false, NAKed if true.
242 *
243 * \return Boolean \c true if the byte reception successfully completed, \c false otherwise.
244 */
245 bool TWI_ReceiveByte(TWI_t *twi, uint8_t* const Byte,
246 const bool LastByte) ATTR_NON_NULL_PTR_ARG(1, 2);
247
248 /** High level function to perform a complete packet transfer over the TWI bus to the specified
249 * device.
250 *
251 * \param[in] twi The TWI Peripheral to use
252 * \param[in] SlaveAddress Base address of the TWI slave device to communicate with.
253 * \param[in] TimeoutMS Timeout for bus capture and slave START ACK, in milliseconds.
254 * \param[in] InternalAddress Pointer to a location where the internal slave read start address is stored.
255 * \param[in] InternalAddressLen Size of the internal device address, in bytes.
256 * \param[in] Buffer Pointer to a buffer where the read packet data is to be stored.
257 * \param[in] Length Size of the packet to read, in bytes.
258 *
259 * \return A value from the \ref TWI_ErrorCodes_t enum.
260 */
261 uint8_t TWI_ReadPacket(TWI_t *twi,
262 const uint8_t SlaveAddress,
263 const uint8_t TimeoutMS,
264 const uint8_t* InternalAddress,
265 uint8_t InternalAddressLen,
266 uint8_t* Buffer,
267 uint8_t Length) ATTR_NON_NULL_PTR_ARG(1, 4);
268
269 /** High level function to perform a complete packet transfer over the TWI bus from the specified
270 * device.
271 *
272 * \param[in] twi The TWI Peripheral to use
273 * \param[in] SlaveAddress Base address of the TWI slave device to communicate with
274 * \param[in] TimeoutMS Timeout for bus capture and slave START ACK, in milliseconds
275 * \param[in] InternalAddress Pointer to a location where the internal slave write start address is stored
276 * \param[in] InternalAddressLen Size of the internal device address, in bytes
277 * \param[in] Buffer Pointer to a buffer where the packet data to send is stored
278 * \param[in] Length Size of the packet to send, in bytes
279 *
280 * \return A value from the \ref TWI_ErrorCodes_t enum.
281 */
282 uint8_t TWI_WritePacket(TWI_t *twi,
283 const uint8_t SlaveAddress,
284 const uint8_t TimeoutMS,
285 const uint8_t* InternalAddress,
286 uint8_t InternalAddressLen,
287 const uint8_t* Buffer,
288 uint8_t Length) ATTR_NON_NULL_PTR_ARG(1, 4);
289
290 /* Disable C linkage for C++ Compilers: */
291 #if defined(__cplusplus)
292 }
293 #endif
294
295 #endif
296
297 /** @} */
298